AMD Athlon II X4 Quad-Core Processor family in Delhi
amd athlon ii x4 651 / amd athlon ii x4 640/amd athlon ii x4 641 /amd athlon ii x4 640 /amd athlon ii x4 638 / amd athlon ii x4 631
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An award-winning technology designed to reduce bottlenecks that can exist when multiple components compete for access to the processor bus. Competing x86 systems use a single front-side bus (FSB) which must carry memory access, graphics, and I/O traffic. Eliminate the FSB, and you can reduce delays that competing access requests can cause.
Doubles processor bandwidth from 64- to a full 128-Bit Floating-Point math processing pipeline that can double many of the bandwidth paths that help keep it full.
Provides support for SSE, SSE2, SSE3, SSE4a, and MMX instructions for digital media applications and security.
The extensive AMD64 architectural optimizations and features enable thorough integration of multiple cores within the same processor, with each core having its own L1 and L2 caches.
Each core has its own dedicated L2 cache, which enables simultaneous independent core access to L2 cache, eliminating the need for cores to arbitrate for cache access. This helps reduce latency on L2 cache accesses.
Silicon feature-set enhancements designed to improve the performance, reliability, and security of both existing and future virtualization environments.
The latest power management technologies that deliver performance on demand when you need it, and power savings when you don't.
AMD64 technology enables a breakthrough approach to 64-bit computing that doubles the number of registers in the processor and allows PC users to use today’s 32-bit software applications while enabling them to also use the next generation of 64-bit applications.
Up to eight different performance states help enhance power efficiency. Simplified performance state transitions can reduce latency and the software overhead of performance state changes.
Each processor core, and the integrated memory controller and HyperTransport™ controller, is powered by dedicated voltage planes.
Directly connects the processor to memory for optimum performance, low latency, and high throughput.
The next-generation design features multiple on-die thermal sensors with digital interface. Automatic reduction of p-state when temperature exceeds pre-defined limit. Additional memory thermal management interface.
Coarse and fine transistor control that can automatically reduce processor energy consumption by turning off unused parts of the processor.
|Model Number||Frequency||CMOS Technology||Total Dedicated L2 Cache||Packaging||Thermal Design Power|
|651||3.0 GHz||32nm SOI||4MB||socket FM1||100W|
|645||3.1 GHz||45nm SOI||2MB||socket AM3||95W|
|641||2.8 GHz||32nm SOI||4MB||socket FM1||100W|
|640||3.0 GHz||45nm SOI||2MB||socket AM3||95W|
|638||2.7 GHz||32nm SOI||4MB||socket FM1||65W|
|631||2.6 GHz||32nm SOI||4MB||socket FM1||100W|
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